Re: [CAD_CAM_EDM_DRO] Parallel port relay blues

Hi Roy,

You're right! What WAS I thinking. My configuration requires an
inverting gate in order to be active low. 74LS04 or something. Or an
opto-isolator. An "active low" signal would probably be more noise immune.

Alan KM6VV


Roy J. Tellason wrote:

> On Saturday 29 January 2005 09:30 pm, Alan Marconett wrote:
>
>>Hi Bert,
>>
>>Are you tying one end of the relay to +5, and the collector to the other
>>end? The output gate of the parallel port is "sinking" current in this
>>case.
>
>
> Not! Collector to relay (with +5 on the other end), emitter presumably
> grounded, and the base going to a port pin with a resistor is *only* going
> to be active when that port pin is high -- and therefore _sourcing_ current,
> something they don't do all that well. If it were a circuit configuration
> with say the inversion of the above arrangement, using a PNP transistor
> (2N2907 comes to mind as the opposite number of the 2N2222), emitter to +5,
> collector to relay coil, other end of which is _grounded_ then the base to
> port pin through a resistor, THEN we would have a setup which would be
> active when the port pin went _low_, and therefore would be _sinking_
> current.
>
>
>> More current is available then "sourceing" current.
>>
>>Alan KM6VV
>>