Re: [CAD_CAM_EDM_DRO] Hardware step generator idea

Chris Stratton wrote:

>
> Actually they are 16 bit. In the original pc the clock to the 8253
> was 1.19 mhz, which when divided by 65536 gives the 18.2 hz timer tick.
>
> I do see the potential problem, though. With a 10mhz clock you get
> decent timing at 100 khz step rates (roughtly 1khz steps) but the
> minimum step rate is 152 Hz. Still, 152 Hz is well below the cycle
> time of EMC, so it would be entirely reasonable to switch to discrete
> pulses at that range.
>
> OTOH, the 24 bit counters probably aren't that much more expensive and
> would make the software simpler.

I do it all in a Xilinx FPGA, which is certainly the way to build anything
more complicated than a couple flip-flops or a one shot. It also allows me to
prototype many circuits with existing boards, just by making a new serial
PROM to download the new gate pattern.

Jon