Re: [CAD_CAM_EDM_DRO] Way OT, Looking for a good ASIC house
Posted by
Jon Elson
on 2001-11-23 20:55:47 UTC
mariss92705@... wrote:
CPLDs are very low in cost, and can put an amazing amount of logic
on a small, inexpensive chip. I use Xilinx, both the XC9500 family of
EEPROM CPLDs and the XCS (Spartan) series of FPGAs. I don't
know how complex your design is, 10K gates sounds way high for
what I know a gecko drive does now. 2K gates is well within the
capacity of the smallest XC9500 CPLDs, and these are in the $6
range. An XC9572 has 72 FFs and 1600 usable gates, and can
clock up to 100 MHz or so. These chips can be programmed on
the final system board through a 4-pin interface. This might be
useful for loading a test program that verifies the unit before
the final user program is loaded. The chip can also be reprogrammed
for firmware updates. (The configuration can be locked so
it can only be erased, not read out, for IP security.)
You can program these things with $500 software from Xilinx in
VHDL, state machine diagrams, or schematics - or a mixture of
all three. They also have some free software on the web.
http://www.xilinx.com/
Jon
> Hi,I should have included this other point in my first response. FPGAs and
>
> I know a lot of people on the list are involved with the
> semiconductor industry.
>
> What I am looking for is recommendations for a good custom or semi-
> custom ASIC design/supplier that utilizes a metal gate CMOS process.
>
> I have in mind a long term (1 year) project that would involve the
> integration of our present 4000 series CMOS based drive logic as an
> ASIC component. Complexity would be in the 2K to 10K gate range, and
> I am aware of the costs involved.
CPLDs are very low in cost, and can put an amazing amount of logic
on a small, inexpensive chip. I use Xilinx, both the XC9500 family of
EEPROM CPLDs and the XCS (Spartan) series of FPGAs. I don't
know how complex your design is, 10K gates sounds way high for
what I know a gecko drive does now. 2K gates is well within the
capacity of the smallest XC9500 CPLDs, and these are in the $6
range. An XC9572 has 72 FFs and 1600 usable gates, and can
clock up to 100 MHz or so. These chips can be programmed on
the final system board through a 4-pin interface. This might be
useful for loading a test program that verifies the unit before
the final user program is loaded. The chip can also be reprogrammed
for firmware updates. (The configuration can be locked so
it can only be erased, not read out, for IP security.)
You can program these things with $500 software from Xilinx in
VHDL, state machine diagrams, or schematics - or a mixture of
all three. They also have some free software on the web.
http://www.xilinx.com/
Jon
Discussion Thread
mariss92705@y...
2001-11-23 17:45:03 UTC
Way OT, Looking for a good ASIC house
JanRwl@A...
2001-11-23 18:26:39 UTC
Re: [CAD_CAM_EDM_DRO] Way OT, Looking for a good ASIC house
Jon Elson
2001-11-23 20:47:03 UTC
Re: [CAD_CAM_EDM_DRO] Way OT, Looking for a good ASIC house
Jon Elson
2001-11-23 20:55:47 UTC
Re: [CAD_CAM_EDM_DRO] Way OT, Looking for a good ASIC house