Re: [CAD_CAM_EDM_DRO] Way OT, Looking for a good ASIC house

mariss92705@... wrote:

> Hi,
>
> I know a lot of people on the list are involved with the
> semiconductor industry.
>
> What I am looking for is recommendations for a good custom or semi-
> custom ASIC design/supplier that utilizes a metal gate CMOS process.
>
> I have in mind a long term (1 year) project that would involve the
> integration of our present 4000 series CMOS based drive logic as an
> ASIC component. Complexity would be in the 2K to 10K gate range, and
> I am aware of the costs involved.

We are doing ultra low noise linear circuits on an AMI CMOS process,
through the MOSIS service. We design the chips, they get a bunch of
designs onto one reticle and have a couple wafers made at AMI. About
10 weeks later, we get chips. If you want low density, you can have
"tiny chips" (2.2 x 2.2 mm) made on the 1.5 uM process for $980.
You get 5 chips for that price. With digital logic, you can probably get
several thousand gates for that price, but you probably can't get 10K
gates into a tiny chip. This is a 5 V process, so if you are counting on
running 12 V on the chip, that could be a problem. I'm not sure any
MOSIS process has metal gates, why do you think you need them?

We are using the .5 uM AMI process at .6 uM minimum feature size.
This has an extra metal layer and high resistance poly layer, very good
for linear circuits. But, it is a lot more compact and faster than the
1.5 uM process. The minimum chip size is 5 mm^2, so you end up
blowing over $6000 a run. Even with totally digital logic, you are likely
to need more than one try at it before it works the way you want.
After some experience, you get to know how to specify things so
the simulations actually prove out the design to meet your needs.

Once you get the design right, MOSIS can have a dedicated wafer run
just for you, and the per-piece price goes WAY down. Maybe down
to a couple $ per chip, if they are small.

As for design, I don't know anyone. We have 2 universities here that
do chip design as student projects. So, for funding a grad student
and some part of a professor, we get a chip made, and they get
a thesis written. Then, we see what worked and what didn't, and we
do it again. We are on the 4th prototype, now, and it is coming along
well.

For MOSIS, see http://www.mosis.org

Jon