Re: Re: Smart/Dumb box again... (CPU timing)

On 28 Feb, CAD_CAM_EDM_DRO@yahoogroups.com wrote:

> Subject: Re: Smart/Dumb box again... (CPU timing)
>
> Alan,
>
> Not sure if I'll actually work on implementing this or not, but I'd
> like to keep time in terms of clock cycles on the CPU - similarly to
> how some PICs have a timing register incremented each cycle.

Oh, do have fun with that x86 ASM code.

And understand that what unless you have the Intel uP manual for the
processor you're using AND you have the datasheets on the chipset for
the motherboard you're using AND you have BIOS code to understand how
those support chips are initialized, you have no idea how long your
loops are going to take !

For example, your

JMP Shift

instructions will take MORE CPU cycles on a 486 than a 386, more still
on a Pentium and most of all on a PII ( the first time ).

This is because the JMP instruction causes the prefetch queue to be
flushed, effectively stalling the uP until the queue is refilled.
Longer queues result in better performance - until they're flushed, when
longer queues then hurt performance.

Subsequent iterations may be fast or slow on the PII ( and newer ) as
branch prediction logic can then be used to fill an alternate queue,
although sometimes the processor guesses wrong.

Gets weirder still with any processor implementing "speculative"
execution. With these processors, subroutines can appear to execute in
ZERO clock cycles as another area of the CPU may be performing those
nondependent calculations in parallel with the main thread. Should that
sub be jumped to, the calculations may already be complete.

God forbid you try to time an I/O input or output, or even a memory read
or write. They just can't be counted on. The days of taking out
the TASM guide and putting clock cycle counts besides instructions was
mostly over with the 386 and is certainly nonsensical with the Pentium.

If there is one big difference between classical microPROCESSORs and
microCONTROLLERs, it is determinism - knowing EXACTLY how long things
are going to take. Unfortunately, even that's disappearing as more and
more of the manufacturers are introducing uP cores with lots of I/O
latches and calling them uCs - they are and they aren't. Yes, they have
direct I/O, but no, you have no good idea how long things are going to
take.

Anyway, have fun.

Alan

--

Alan Rothenbush | The Spartans do not ask the number of the
Academic Computing Services | enemy, only where they are.
Simon Fraser University |
Burnaby, B.C., Canada | Agix of Sparta