Re: [CAD_CAM_EDM_DRO] Enocders and stepper feedback method?

daque@... wrote:

> Anyone ever consider something like this?
>
> 1)Have an 8 bit counter that counts both the encoder outputs and the
> requested steps.
>
> 2) start the count at 128
>
> 3)If the ratio of encoder(x4) to stepper pulses is for example
> (2.5pulses/step) and if cw rotation is considered positive add 5 to
> the count for each cw stepper pulse requested, subtract 2 for each cw
> encoder count received.
>
> 4) If the count gets to 130, ( >1/2 step ) step the motor 1 step CW.
> the same for ccw, if < 126 step the motor ccw.
>
> No need for a 32 bit counter and you still could have up to 24 steps
> missed and it still catch up. It would seem lots of ratios of encoder
> to stepper could be used by just changing the values for both count
> increments and the up and lower step points.
>
> I am trying to figure out how to do that with a PIC chip. The problem
> I see is the random timing of the pulses would likely end up loosing
> a step now and again. I will likely need a pic and another chip.
>
> I just wanted to bounce this off the list, to see what you guys thing
> of the general approach. Sound like a reasonable thing to try?

There are so many 'logic hazards' associated with doing this with
a CPU of any sort. The interface between systems with different
clocks, or between a clocked system (the CPU) and a system with
random timing (encoder connected to a motor) plus some electrical
noise can make it real difficult to be sure you never lose a pulse.

I designed a device that did it all, with rigorous attention to all logic
hazards. It was NOT simple at all. For each channel, it has a quadrature
encoder counter (with index pulse for precise homing) and a digital
rate generator which allows step rates from .6 Hz to 300 KHz with
100 nS resolution. That takes a 24-bit counter. This makes it possible
to produce extremely smooth acceleration and deceleration ramps,
as well as smooth pulse trains at any desired rate, with minimal pulse
jitter. This would be impossible with any reasonable CPU.

I also added a bunch of logic to each channel to allow pulses to be
delayed for a settable delay after the direction signal changes, and to
delay direction changes for a settable delay after a step pulse.
This logic also took a bit of careful thinking to get right.

The step rate generators generate step/direction signals as well
as 2-phase bipolar stepper drive signals, for step drivers that need
those signals. As it happens, those signals are identical to a quadrature
encoder, so they can be fed into the encoder input if you are not
using encoders.

I was able to pack 4 axes worth of this logic, plus digital I/O (16 in,
8 out) onto one Xilinx FPGA. This chip costs about $45, but it is all
the logic on the board. The remaining parts are a crystal oscillator
and a bunch or optocouplers and SSRs.

I am still fighting the changes in EMC to get both the digital I/O and
the motion control funneled through the same code so one activity
doesn't garble the other one. This all connects to one parallel port.

Jon