Re: [CAD_CAM_EDM_DRO] Re: Does control s/w affect machine performance? max step rate

Mariss Freimanis wrote:

>Art put it very well.
>
>The "quality" of the step pulses really matters for how much power
>you will get from a motor. "Ragged" pulse timing robs motors of
>torque that could be applied to a load. Instead it wastes it on
>pointless accel/decel torque loads.
>
>Perfect pulses are evenly spaced at any speed. This never happens in
>the digital world though you can come very close.
>
>Barring anything else, a pulse generator that can generate
>extraordinary step pulse rates can also be depended on to produce
>very evenly spaced ones at lower speeds.
>
>But how about if you really need high pulse frequencies, what would
>the conditions be? Let's say you have a 1,000 line encoder on a servo
>motor that has a 6,000 RPM rated speed. 1,000 lines means 4,000
>counts per revolution; 6,000 RPM is 100 revs/sec, so it would take
>100 times 4,000 or 400,000 step pulses per second to get what you
>need.
>
>

Well, I could up the clock on my USC board and have no trouble going there.
It will do 300,000 steps a second now, with 100 nS resolution. I'm only
clocking the FPGA at 10 MHz, so the chip is loafing. Really, all I have to
do is up the clock to the encoder counter (which raises the cutoff frequency
of the digital filter on the encoder). The 10 MHz clock is probably still
fast enough for 400 KHz (~ 4% jitter).

>Or how about you have a Compumotor drive set a 125 microsteps per
>step and you need 3,000 RPM. That's 50 revs/sec at 25,000 counts per
>rev or 1.25MHz for a pulse rate. Suddenly a 4MHz pulse rate doesn't
>seem too high. Comfortable but not too excessive as a matter of fact.
>
>

I can probably still do that with my board. But, that is starting to get a
little harder. Clearly, the clock has to be higher than 10 MHz, maybe 40
would work. That would keep jitter at about 3%.

>
>

Jon