Re: Pulse Gen

--- In CAD_CAM_EDM_DRO@egroups.com, Jeff Barlow <jeff@b...> wrote:

Hi,

"Never" I can't design for, 20 ms I can. If a FIFO buffer is used
then interrupts in the classic sense are not needed. A 2 kbyte FIFO
buffer would hold a 1/4 second worth of data for 4 axies. Couldn't
this be polled and topped-off 4 to 5 times a second?

Mariss


>
> Hi Mariss,
>
> The worst case interrupt latency on a PC is more like infinite.
That is,
> some just get lost. As I said in my off list message to you: "For
any PC
> device driver to work reliably it must be designed to tolerate
missing
> interrupts." Not just late, missing. This is not just a Windows
problem,
> but Windows makes it worse. The underling problem is bad hardware
and
> BIOS design.