Re: [CAD_CAM_EDM_DRO] Allegro delay
Posted by
Jon Elson
on 2001-06-03 11:34:40 UTC
lonnietoons@... wrote:
a diode in parallel with it, and a capacitor to ground at the input of the
driver chip. Assuming the Allegro UDN2961 has CMOS inputs, you
can use a 5.1 K Ohm resistor in series, and 680 pF cap to ground
to get about the right delay. If the inputs are high=on, then you want it
to go low faster than it goes high, so you want the diode with the
cathode (bar end) facing toward the signal source, and the anode end
facing the 2961 driver chip. If the input is low=on then reverse the
diode. If the 2961 is not a CMOS input, the resistor value will have to
be lower, and the capacitor larger to get the 3 uS delay.
| |
| /|
| / |
-------| / |--------
| | \ | |
| | \ | |
| | \| |
| | | |
| |
| / / / |
from ---------/ \ / \ / \------------- to UDN2961
logic \ \ |
input |
|
-------
Bad ASCII Cap
---
/ | \
|
|
-----
- Gnd
.
Jon
> Hi Everybody,I did the same in a PWM servo amp. I used a series resistor and
> I am putting together some PWM drives using 4 Allegro UDN2961W chips
> for each drive. 2 are cross connected to form a full bridge. In their
> application info it says "In order to prevent cross-over currents, a
> turn-on delay time of 3us is needed between the time an input signal
> for one of the half bridges goes high and the inpput signal for the
> other half bridge goes low." I am not that experienced with
> electronics to know how to accomplish this. Can somebody recommend
> a way for me to do this? I have figured out I can use the Allegro
> 5804 unipolar driver to give me the proper steping signals. Is it
> possible that the 5804 already has a delay built in going from step
> to step?
a diode in parallel with it, and a capacitor to ground at the input of the
driver chip. Assuming the Allegro UDN2961 has CMOS inputs, you
can use a 5.1 K Ohm resistor in series, and 680 pF cap to ground
to get about the right delay. If the inputs are high=on, then you want it
to go low faster than it goes high, so you want the diode with the
cathode (bar end) facing toward the signal source, and the anode end
facing the 2961 driver chip. If the input is low=on then reverse the
diode. If the 2961 is not a CMOS input, the resistor value will have to
be lower, and the capacitor larger to get the 3 uS delay.
| |
| /|
| / |
-------| / |--------
| | \ | |
| | \ | |
| | \| |
| | | |
| |
| / / / |
from ---------/ \ / \ / \------------- to UDN2961
logic \ \ |
input |
|
-------
Bad ASCII Cap
---
/ | \
|
|
-----
- Gnd
.
Jon
Discussion Thread
lonnietoons@y...
2001-06-03 08:04:44 UTC
Allegro delay
Jon Elson
2001-06-03 11:34:40 UTC
Re: [CAD_CAM_EDM_DRO] Allegro delay
lonnietoons@y...
2001-06-04 10:27:37 UTC
Re: Allegro delay
Jon Elson
2001-06-04 12:15:30 UTC
Re: [CAD_CAM_EDM_DRO] Re: Allegro delay
lonnietoons@y...
2001-06-05 05:31:04 UTC
Re: Allegro delay