Re: [CAD_CAM_EDM_DRO] Re: Allegro delay

lonnietoons@... wrote:

>
> Thanks Jon for helping me out with this. I see I should have
> specified that the chips need a logic low to turn on and they are
> cmos. I was thinking a 10k resistor would hold each chip high. Should
> this 10k plug into the Udn2961 side of the RC combo or the logic
> input side? This is what I am thinking it should look like:
>
> |\ | +5v
> | \| |
> -------| /|------- /
> | |/ | | \10k
> | | /
> | 5.1k | \
> logic in --------/\/\/\---------------|-------- to UDN2961
> (5804 sinks |
> to ground) |
> -------
> ------- 680 pf cap
> |
> gnd

No, this may not work. The pullup should be on the driving side of
the network, and should be much lower than 10K so that a fast rise
is developed to quickly turn off the driver that is on. If the 10K is at
the output, then it creates a voltage divider such that the input to
the UDN2961 can only be lowered to about 1.6 V, which is probably
a forbidden level. Put a 510 Ohm or so resistor pullup at the output
of the 5804 and you should get proper operation.

Jon