Re: [CAD_CAM_EDM_DRO] Re: potential product

jeffalanp wrote:

>Hi Jon,
> You are correct, the Xylotex three axis board is not opto-isolated.
>
> I'm pretty sure your system would work with the requirements of the
>chipset(Allegro), but a note: the logic high input is not exactly
>TTL. To be detcted as a 1, the voltage needs to be at .7V * Vcc.
>Typically Vcc is at 5.0V, so a logic 1 would need to be 3.5V A few
>users did have some problems reaching this value with low power built-
>in motherboard parallel ports. If you drive to almost 5V there
>would be no problem.
>

I'm using a 5 V CMOS FPGA. Unless the chips at the input of the Xylotex
draw significant current at the high logic level, the FPGA will have no
trouble delivering 4+ V to it.

> The board responds to rising edge STEP signals. The DIR line must
>be stable 200ns before and after the rising edge, and the STEP
>signals must be valid for at least 1uS.
>
>

Ahh, those are very nice setup and hold requirements, and my board
already will do that VERY nicely.

Jon