Re: [CAD_CAM_EDM_DRO] Re: PC based CNC system architecture

Wally K wrote:

> Wally K. replys:
>
> If you give out the complete details of the hardware/software
> interface and what the registers look like from the CPU end, sample
> programs, and the EMC code. I think that would go a long way to
> remove the stigma of a closed system. I will not ask you to give up
> your FPGA design if you do not want to. But i would ask you to sell
> the programmed chip for others to use in there designs.

The register def is attached.

> Wally K. replys:
>
> This was kind of what i was getting at. You have made a specific
> design for 1 customer and now everyone has to live with those wants
> and needs.

Yes, but so did the guys who designed the LS7166 and 7266.

>
> > >Wally K wrote:
> > >
> > > 3) it will be fairly expensive. From memory $350.00 or so.
> >
> >Jon Elson wrote:
> >
> > The particular customer wanted nice Phoenix Contact plug-in
> > terminal blocks, and some other stuff that ran up the cost, also
> > needed differential input option, etc...
> >
> > A different design should be able to be done using the same basic
> > chip such that the entire counter and rate generator would fit on
> > one board. I think the only other part would be the crystal
> > oscillator. We also did a fancy 8-slot motherboard for these
> > cards, but again, there are much cheaper ways to go, like
> > eliminating the gold card edge fingers.
> >
> > These prices were based on buying 15 PC boards, first time
> > (so it incurs the setup charge) and parts for about 5 of each
> > board. Even small increases in volume make a big difference,
> > especially in the PC board cost.
> >
> > Jon
>
> Wally K. replys:
>
> Jon you have been with this group far longer than i have. From your
> experience with this group wouldn't you say the people here range
> from thrifty to cheap (not that there is anything wrong with being
> either).
>
> After reading Matt Shaver's post about selling this unit for $800.00
> to $1000.00 i darn near fell off of my chair. I would say with that
> price Matt has put this control out of reach of at least 90% of the
> people that would want it.
>
> I would really like to see your schematic of this control with the
> sections needed for stepper control marked. I would like to see if i
> could make a new layout and or make different component choices for a
> low cost stepper control.

The first batch of boards cost $57 each! Now, if we don't need to revise
them, and we buy a larger quantity on a reorder, we save a bundle!
About the only component change you can make is the terminal
strips. There are $36 of Phoenix Contact pluggable screw terminals
on this version. Much cheaper terminals should be available, although
these are 2.5 mm spacing in this design. The only other expensive
part is the Xilinx XCS10-PC84C FPGA, at $18.10 (and I was forced
to buy 15 of them!) There is a $6 SPROM to load the configuration
into the FPGA, one 74HC00 gate for startup and a crystal oscillator module.
That's all there is on the board, if you don't want differential inputs.
This and a few decoupling caps comes to $126 - it adds up quick.

I added a few extra traces on the board so that the same board could
be used with a different chip configuration as a 4-channel rate generator.
That is still a concept only, but I'm pretty sure I can make it work in
the same FPGA.

Jon

----------

Description of Pico Systems Parallel Port Motion Control
boards from a register perspective.

********************************
Encoder Counter Board

Address Read Write
0 Axis 0 low byte Assembly Register low byte
1 Axis 0 mid byte Assembly Register mid byte
2 Axis 0 hi byte Assembly Register hi byte
3 Axis 1 low byte Control Register
4 Axis 1 mid byte Timer config Register
5 Axis 1 hi byte
6 Axis 2 low byte
7 Axis 2 mid byte
8 Axis 2 hi byte
9 Axis 3 low byte
10 Axis 3 mid byte
11 Axis 3 hi byte
12 Index Sense Register
13, 14, 15 not used

The axis read registers are a 24-bit straight binary up/down
counter broken into three bytes. The MSB contains a normal,
2's complement sign. This value represents the count of
edges of the quadrature waveform coming in the A and B inputs
to the board from the encoders. This 24-bit value has been
latched into a holding register, so there will be no mis-reading
of the value due to encoder counts being received during the
read of the three bytes.

The Holding Register is a 24-bit register that assembles a
24-bit value from 3 bytes input to the board. When the 3
bytes have been assembled, they can be loaded into one of the
counters through the control register.

Control Register Bits :
Bit # 7 6 5 4 3 2 1 0
Axis # 3 2 1 0 3 2 1 0
Function ---Load Position--- ---Index Select----

The load position bits will cause that axis's encoder
counter to load the 24-bit value now in the assembly
register. This bit needs to be set to a one, and then
cleared back to zero.

The Index select bit, when 1, will cause that axis's 24-bit
latch to only latch the encoder count when the index pulse is
sensed from the encoder. It will latch on the rising edge
of the index pulse. This will also set the index sense
bit in the index sense register. If the Index Select bit
is 0, then the latch will latch the count every time the
Intr bus signal is asserted. The master encoder counter
board will assert this line every time the timer generates
a pulse.

Timer Register Bits :
Bit # 7 6 5 4 3 2 1 0
Function none none soft master tim3 tim2 tim1 tim0
latch

Description of Timer Register Bits :
SoftLatch - when there is no 'master' encoder, then
writing a 1 to this bit generates a software controlled
latching of the encoder counts. Write a 0 after writing
the 1.

Master - Setting this bit to 1 selects this encoder counter
as the master board, such that it drives the bus Intr
line to cause any other encoder counters to also latch
the count, and any DAC16 boards to update the analog value
from the holding registers. Leaving this bit at 0 (power
on default) causes the board to accept the Intr signal
from other units.

TIM(3:0) These select the count down divisor from a 10 KHz
clock. 1111 means don't divide, so the encoder will be
latched every 100 uS (10 KHz). The counter counts up to
1111 from whatever value is entered, so a setting of 0110
(6) will go through 10 states before automatically reloading
this value. Therefore, loading 6 here will make the
encoders latch at a 1 KHz rate.


Index Sense Register Bits :
Bit # 7 6 5 4 3 2 1 0
Axis # 3 2 1 0

The 4 LS bits are a latch for sensing of the index pulse.
The axis must have the index select bit turned on in the
control register, and this register must be read once
(which clears it after the read) before the values are
meaningful.

Addressing the module :
This board accepts an address on the 4 LS bits of the
data bus during assertion of ADDRSTB on the EPP bus
to select which register will be read or written.
The 4 MS bits are used to select which board is addressed.
The convention, at present, is to have the first encoder
counter at address 0000xxxx, and the 2nd board, if any,
at 0001xxxx.
After each data byte is transferred, the internal address
counter increments. You can select the first address in
the board (first addr in first board would be 00000000 )
and then read all 12 bytes (3 bytes x 4 axes) with 12
consecutive read data operations, causing the DATASTB
line to pulse.

********************************
DAC-16 board

This board contains 4 16-bit DACs. It works in a manner similar
to the one described above, for addressing from the EPP port.
The DAC in question, the Burr Brown DAC7644, has the capability
to read back what is in the DAC's data register. it also has
the capability to hold the digital data as it is entered, and
only transfer it to the actual D/A converters on a strobe signal
given later.

These are the addresses on the board :

Addr Function
0 chan 0 low byte
1 chan 0 high byte
2 chan 1 low byte
3 chan 1 high byte
4 chan 2 low byte
5 chan 2 high byte
6 chan 3 low byte
7 chan 3 high byte
8 write anything loads data into dac
9 - 11 no function
12 select Load DAC mode

If a 0 is written to reg 12, then the loading of data to the DAC
is controlled by a pulse on the INTR EPP bus line. This is intended
to be generated by the timer on the master encoder board.
If a 1 is written to that register, then the loading of data to
the DAC is commanded by writing anything to reg 8. This is
conveniently set up so that it can be written right after
writing the last data byte to reg 7.

As on the encoder board, the first register to be addressed is
written with an ADDRSTB signal with the address of the board and
desired register on the data lines. Then, registers can be
read or written sequentially by pulses on the DATASTB line.

The data format is as follows :
+10 V output 0xFFFF
0 V 0x8000
-10 V 0x0000




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