Re: [CAD_CAM_EDM_DRO] Re: Re: Smart/Dumb box again... (CPU timing)

beer@... wrote:

> On 28 Feb, CAD_CAM_EDM_DRO@yahoogroups.com wrote:
> > Subject: Re: Smart/Dumb box again... (CPU timing)
> >
> > Alan,
> >
> > Not sure if I'll actually work on implementing this or not, but I'd
> > like to keep time in terms of clock cycles on the CPU - similarly to
> > how some PICs have a timing register incremented each cycle.
>
> Oh, do have fun with that x86 ASM code.
>
> And understand that what unless you have the Intel uP manual for the
> processor you're using AND you have the datasheets on the chipset for
> the motherboard you're using AND you have BIOS code to understand how
> those support chips are initialized, you have no idea how long your
> loops are going to take !
>
> For example, your
>
> JMP Shift
>
> instructions will take MORE CPU cycles on a 486 than a 386, more still
> on a Pentium and most of all on a PII ( the first time ).

Yes, you really can't run timing loops on any processor with cache (especially
multi-level cache), branch prediction, deep pipelining, etc. as the time the loop takes
to execute can vary 100 : 1 ! And, you really have no way of knowing what time
the loop will take any time, as it depends not only on the past history of what code
was executed last, but on what guesses the cache and branch prediction hardware
made about what to do next or load into the cache.

Jon